Many-core processors with on-die network-on-chip (NoC) interconnects are emerging as viable architectures for energy efficient high performance computing (HPC). Aggressive supply voltage scaling of these processors can result in higher energy efficiency. However this efficiency comes at the expense of processor performance loss. To compensate for this performance loss, many-core processors try to parallelize workloads across more cores. Future trends for energy efficiency expect more small cores integrated on a single die, larger die sizes for increased parallel performance, and lower operating voltages for increased energy efficiency. While technology scaling and the quest for increased energy efficiency have fueled the growth of many-core processors, the effects of core-to-core variations in maximum clock frequency (Fmax) and power leakage due to parameter variations among cores become significant.
To accommodate the variations among different cores in a many-core processor, current art runs the many-core processor according to the capacity of the least capable core to prevent causing errors during execution. For example, all of the cores on the many-core processor run at the maximum clock frequency (Fmax) of the slowest core so that all of the cores may safely execute codes. However, this approach does not use all of the cores to their full capacities, thereby resulting in sub-optimal energy efficiencies.